1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor memory device testing method and, more particularly, to a double data rate synchronous dynamic random access memory (DDR SDRAM) and a testing method thereof.
2. Description of the Background Art
Semiconductor memory devices have their performance verified by a testing device called tester at a final stage of their production process.
FIG. 15 is a diagram for use in explaining performance verification by a conventional tester.
With reference to FIG. 15, a tester 202 applies, to a memory device 204 to be tested, control signals /RAS, /CAS, /WE, an address signal ADD and a data input signal DIN to observe a data output signal DOUT output by the memory device 204.
The tester 202 includes a timing generator 206 for generating a timing reference signal for the test, a signal generator 208 for outputting the control signals, the address signal and the data input signal in response to the output of the timing generator 206, and a determination 210 for observing the data output signal DOUT output by the memory device 204 with the output of the timing generator 206 as a reference of time to determine whether the memory device 204 operates normally.
FIG. 16 is an operation waveform diagram for use in explaining a conventional performance verification test of a semiconductor memory device.
With reference to FIGS. 15 and 16, at time t1, the tester 202 causes the control signal /RAS to fall, so that the memory device 204 accepts a row address signal X. Then, The control signal /WE is set at a logical low or xe2x80x9cLxe2x80x9d level by the tester 202 and the memory device 204 is supplied with data DATA to be written by the data input signal DIN.
At time t2, the control signal /CAS is caused to fall and the memory device 204 responsively accepts a column address Y. Then, the memory device 204 writes the write data DATA in a memory cell designated by the row address and the column address.
Such writing cycle will be repeated as many times as the number corresponding to the memory capacity.
Next, a reading cycle for reading data will be described. When data writing ends, the control signal /RAS is caused to fall at time t3, so that the row address X is accepted into the memory device 204. Subsequently, the control signal /WE is set at a logical high or xe2x80x9cHxe2x80x9d level to designate data reading of the memory device 204.
At time t4, the control signal /CAS is caused to fall, so that the column address Y is accepted into the memory device 204.
Responsively, at time t5, from the memory cell designated by the row address X and the column address Y, the read data DATA is transmitted as a data output signal from the memory device 204 to the tester 202. Determination is made by the determination unit 210 whether the output data coincides with the written data. Thus, determination is made whether the memory device 204 is defective or not.
In recent years, with the speed-up of semiconductor memory devices, there has appeared a synchronous semiconductor memory device whose data input/output is controlled in synchronization with a clock signal, that is, a synchronous dynamic random access memory (SDRAM) and further, a higher-speed DDR SDRAM has appeared which transmits data at a data rate equivalent to both of leading and trailing edges of a clock signal.
FIG. 17 is a waveform diagram for use in explaining one of standards for a DDR SDRAM.
With reference to FIG. 17, the DDR SDRAM outputs a data signal DQ, as well as outputting a strobe signal DQS in synchronization with the data signal DQ. The strobe signal DQS is used as a reference signal for accepting the data signal DQ by a controller or the like, which receives data output by a memory device.
The strobe signal DQS is a signal for use as a solution of a skew between a clock signal and a data signal. Since the data signal DQ and the strobe signal DQS have the same signal transmission direction, skew is reduced. To enhance the effect, a transmission path of the data signal DQ and that of the strobe signal DQS on a printed-circuit board are formed to be approximately equal in length.
With the timing of a rise and a fall of the strobe signal DQS output from the DDR SDRAM as an origin, timing of output of the data signal DQ output similarly by the DDR SDRAM is defined. One of the standards for the timing is called tDQSQ standard.
For example, FIG. 17 shows a case where four data D1 to D4 is successively output from the DDR SDRAM. A time difference between a time of a transition from the data D1 to the data D2 when the data is successively output and a time of the strobe signal DQS is defined by the tDQSQ standard. A time tDQSQmax denotes a maximum allowed time of delay in the data D1 determination behind a time of a rise of the strobe signal DQS. In other words, the data D1 should be defined within a time denoted by tDQSQmax after the time of a rise of the strobe signal DQS and similarly the data D2 should be defined within the tDQSQmax after a time of a fall of the strobe signal DQS.
On the other hand, there is a case where output of the data signal DQ is earlier in time than an edge of the strobe signal DQS. In this case, a time of output of the data D3 should not be earlier by a time denoted by a tDQSQ min than an edge of the strobe signal DQS.
The tDQSQ standard should be satisfied in all the output cycles of data from the memory device. In a case of a 256-Mbit 8-bit-basis DDR SDRAM, the standard needs to be satisfied at each of 32 mega cycles (more precisely 33,554,432 cycles) equivalent to the number of memory cells corresponding to the respective terminals.
It is necessary to examine whether a manufactured device meets this standard or not. In a case of a DDR SDRAM, however, a relative time difference between a strobe signal DQS output and a data signal DQ output should be verified. The strobe signal DQS providing a reference time for the verification has a jitter component with respect to a clock signal applied to the DDR SDRAM. Therefore, the strobe signal DQS is not always output at fixed timing for a clock signal. Tester accordingly needs to simultaneously measure a time of a rise or a fall of the strobe signal DQS and a time when the data signal DQ changes and obtain a difference between the two times to examine the tDQSQ standard.
However, as described with reference to FIG. 14, in a conventional tester, it is a common practice to set a determination reference time according to a timing generator 126 to examine whether the data signal DQ is desired data, that is, a xe2x80x9cHxe2x80x9d level or a xe2x80x9cLxe2x80x9d level is output, from the memory device at the determination reference time. The tester then indicates the result as PASS/FAIL. Thus structured tester has a difficulty in measuring a data signal change point, with such a signal having a jitter component changing every cycle as the strobe signal DQS described in the foregoing as an origin.
Speed and data rate of semiconductor memory devices have been increased year by year. In recent years, higher and higher precision is required of a standard for timing between a strobe signal and data for the purpose of transferring data at a high speed. For example, while demanded precision has been conventionally on the order of nanosecond (ns), recent DDR SDRAM is required to have a precision on the order of picoseconds (ps). In the above-described tDQSQ standard, a precision within 750 ps, for example, is demanded. Under these circumstances, semiconductor manufacturers need to ensure the standard by stringent examination taking a test margin into consideration.
In other words, for an ordinary tester to measure the tDQSQ standard of DDR SDRAMs, the tester should have an extremely high level of performance. As long as a device is defined by the standard, it is necessary to observe whether the device has performance meeting the standard or not.
An object of the present invention is to provide a semiconductor memory device capable of executing a performance test related to a timing standard for a data signal and a strobe signal with ease and a method of testing a semiconductor memory device.
In summary, the present invention relates to a semiconductor memory device having a storage unit and a test circuit. The storage unit includes a plurality of memory cells and successively outputs data held in the plurality of memory cells and outputs a strobe signal whose signal waveform has a leading edge and a trailing edge synchronizing with the data output successively. The test circuit accepts data in response to the strobe signal.
The test circuit includes a first transmission gate unit responsive to a strobe signal to become conductive to transmit data and a first holding unit for holding data transmitted by the first transmission gate unit.
According to another aspect, the present invention relates to a subsidiary device for connecting, to a testing device, a semiconductor memory device which includes a plurality of memory cells and successively outputs data held in the plurality of memory cells and outputs a strobe signal whose signal waveform has a leading edge and a trailing edge synchronizing with data output successively, which subsidiary device includes first, second and third terminals and a test circuit.
The first and the second terminals receive data and a strobe signal from the semiconductor memory device, respectively.
The test circuit accepts data applied through the first terminal in response to the strobe signal applied through the second terminal. The test circuit includes a first transmission gate unit responsive to the strobe signal to become conductive to transmit data and a first holding unit for holding data transmitted by the first transmission gate unit. The third terminal transmits the output of the first holding unit to the testing device.
According to a further aspect of the present invention, the present invention relates to a testing device for testing a semiconductor memory device which includes a plurality of memory cells and successively outputs data held in the plurality of memory cells and outputs a strobe signal whose signal waveform has a leading edge and a trailing edge synchronizing with data output successively, which testing device includes a timing generator, a signal generator, a test circuit and a determination unit.
The timing generator outputs a timing reference for a test. The signal generator outputs a control signal to be applied to the semiconductor memory device and data to be stored therein in response to the output of the timing generator.
The test circuit accepts data in response to the strobe signal. The test circuit includes a first transmission gate unit responsive to the strobe signal to become conductive to transmit data and a first holding unit for holding data transmitted by the first transmission gate unit. The determination unit determines whether the output of the first holding unit coincides with an expected value.
Accordingly, a main advantage of the present invention is to facilitate verification by a testing device that a strobe signal and data have a predetermined relative time relation by latching data at a test circuit in practice.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.